1. Field of the Invention
The present invention relates generally to a field effect transistor and, more specifically, to a highly integrated field effect transistor in which a channel region formed between a drain and a source is opposed to a gate.
2. Description of the Prior Art
FIG. 1 is a schematic diagram showing a silicon gate type n channel MOSFET which is an example of a conventional field effect transistor.
Referring to FIG. 1, in this MOSFET 1, n type impurities are diffused in a p type silicon substrate 2 to form a drain 3 and a source 4. A gate 6 formed of polycrystalline silicon is provided above the channel region 5 formed between the drain 3 and the source 4 with a gate oxide film, not shown, interposed therebetween. Other oxide films, Al wiring and the like are omitted in FIG. 1.
Such MOSFET 1 can be obtained by manufacturing methods such as follows. Namely, (1) n type impurities are doped with a prescribed mask disposed on a main surface 2a of a substrate 2 to form the drain 3 and the source 4, and thereafter, a polycrystalline silicon is provided above the channel region 5 as the gate 6, or (2) a polycrystalline silicon is provided as the gate 6 above the position on which the channel region 5 should be formed, and thereafter, n type impurities are doped with the gate 6 serving as a mask to form the drain 3 and the source 4 by self-alignment.
In the MOSFET 1 having the above described structure, a current flows between the drain 3 and the source 4 through an inverted layer (not shown) generated in the channel region 5 by the voltage applied between the gate 6 and the source 4. The current is controlled by the magnitude of the voltage applied between the gate 6 and the source 4.
According to the conventional MOSFET 1 as described above, the channel surface 5a opposed to the gate 6 for defining the extension of the flow path of the carrier in the channel region 5 is formed in parallel to the main surface 2a of the substrate 2. Therefore, the area S.sub.1 required for forming one MOSFET 1 will be at least approximately: EQU S.sub.1 =(L.sub.C +L.sub.D +L.sub.S).times.D.sub.1 ( 1)
In the equation (1), L.sub.C denotes channel length, L.sub.D and L.sub.S denote length of the drain 3 and of the source 4, respectively, and D.sub.1 denotes channel width.
Therefore, in order to get higher integration of the MOSFET 1 on the substrate 2, the MOSFET 1 itself should be made compact by reducing the channel length L.sub.C, the length L.sub.D and L.sub.S of the drain 3 and the source 4, respectively and the channel width D.sub.1 of each MOSFET 1.
However, the higher integration has difficult problems. Namely, a higher technique of fine processing is required to make compact the MOSFET 1. In addition, in order to maintain the electrical characteristics of the MOSFET 1, the L.sub.C, L.sub.D, L.sub.S and D.sub.1 can not be made very small. These problems are common to all field effect transistors, not only to the MOSFET 1.
Meanwhile, a DRAM cell comprising a trench, a capacitor formed in a lower portion of the trench and a transistor formed in a upper portion of the trench is disclosed in "Technical Digest of International Electron Device Meeting", 1979, Washington D.C., pp. 714-717. However, this structure is also insufficient to improve the degree of integration.